1. Field of Invention
The invention relates to a personal computer system, and more specifically to power management for peripheral component interface (PCI) buses in the personal computer system.
2. Description of Related Art
Generally, power supply is necessary for the operation of an electronic device, and power consumption is an important issue in the performance of an electronic device, especially in a battery-powered personal computer. For a digital electronic instrument, such as a computer system, almost all the components are operated by the application of electrical power as well as a variety of control signals. However, all the components of a normally operated computer system need not always remain in an active mode. Even though some of the components are temporarily powered off, the performance of the computer system is not affected. Therefore, through careful management of the power supply and control signals, a reduction of power consumption of the computer system can be achieved.
There are various buses and peripheral devices in the personal computer which consume a lot of electrical power even in an idle mode. Therefore, various power management arrangements have been developed. For example, a power management unit (PMU) in charge of the power supply and control signals of the components has been developed. The function of the PMU is first to determine when any components are inactive and then to save power by turning off the clock signal to them or by lowering the frequency of the clock signal.
However, although the PMU can reduce the power consumption of the computer system somewhat, it is not easy to connect the PMU with a PCI bus. The main difference between the PCI bus and other bus standards, such as the ISA (Industrial Standard Architecture) bus, EISA (Extended Industrial Standard Architecture) bus and micro channel bus is that the PCI bus has a hierarchical structure. A hierarchical bus structure consists of a plurality of buses arranged in parallel. the problem with the PMU in such a structure is that the PMU tends to misjudge the operating modes of the components, thus failing to keep the computer system operating normally. Referring to FIG. 1 (Prior Art), a hierarchical bus structure is depicted wherein a first PCI bus 60, a second PCI bus 70 and a third PCI bus 80 are connected in parallel through bus bridges (or bus controllers) 33 and 34. The three PCI buses 60, 70 and 80 operate both independently and concurrently. First PCI bus 60 exchanges data with a central processing unit (CPU) 10 and memory devices 12, 14 and 16 through bus bridge 31 and a local bus 50. An ISA bus 90 is connected to first PCI bus 60 through a bus bridge 32. Each of the three PCI buses 60, 70 and 80 is connected to a plurality of peripheral devices for data communication. For example, peripheral controller 21 for VGA signal output is connected to first PCI bus 60, peripheral controller 23 for data exchanging with a primary storage device is connected to first PCI bus 60, and peripheral controllers 26 for a secondary storage device and peripheral controller 27 for connecting a local area network (LAN) are both connected to third PCI bus 80.
The power management unit of standard the hierarchical PCI bus structure is a PMU controller 30 connected to first PCI bus 60. PMU controller 30 sends out a clock signal PCLK to control all the bus bridges and peripheral devices connected directly to first PCI bus 60, while the components on other PCI buses are controlled by reproduced clock signals from bus bridges 32, 33 and 34. In the standard configuration, the PMU would determine whether to turn the clocks of all devices ON or OFF based on the activity status of the first PCI bus but could not consider the status of the other buses. For example although first PCI bus 60 is in the idle mode, it is possible that data exchange between third PCI bus 80 and the LAN is still taking place. If the PMU controller 30 stops sending the clock signal or lowers the frequency of the clock signal when first bus 60 is idle in order to reduce power consumption, the data communication between the computer and the network will be interrupted, thus causing difficulties, such as the loss of data or even the crash of the computer.
Moreover, since PMU controller 30 has no information about the status of local bus 50, to stop sending the clock signal in accordance with the status of first PCI bus 60 may prevent CPU 10 from obtaining data from peripheral controllers through PCI bus 60. Therefore, the computer easily crashes due to the incomplete status detection of other buses by PMU controller 30. This problem can be solved by combining PMU controller 30 and bus controller 31 into a single entity. However the status of ISA bus 90 still can not be detected. That is, the status of local bus 50 and ISA bus 90 can not be sensed by PMU controller 30 at the same time, and thus there is no way to properly control the ON/OFF states of the clock signal, since the PMU cannot monitor the activity of all of the buses.